Our Technologies
Copper Pillar Bump
Molded Interconnect Subtrate (MIS)
No Flow Underfill & Flipchip Packaging
Technical Library
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  1. Assessment of flipchip assy and rel via reflowable underfill
  2. Flip Chip on Leadframe using Copper Pillar Bump Technology
  3. Flipchip assembly development via modified reflowable underfill process
  4. Prebonding flip chip and reliability assessment
  5. Reliability studies flipchip package with reflowable underfill
  6. Studies on a novel flip chip interconnect structure-pillar bump
  7. Studies on reflow underfill for flip chip application
  8. Thermal compression bonding process with low CTE no-flow underfill and copper pillar bump
  9. Wettability studies of reflowable underfill
  10. Wettability studies btw solder bump and subs for reflowable underfill
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